module ctrl(
    input reset,
    input except_ena,
    input [63:0] mtvec_pc,
    input [63:0] epc,
    input ret,
    input stall_from_if,
    input stall_from_mem,
    
    output reg [63:0] new_pc,
    output reg flush,
    output reg [5:0] stall
);

    always @(*) begin
        if(reset) begin
            stall = 6'b000000;
            flush = 1'b0;
            new_pc = 64'd0;
        //end else if(except_ena) begin
        //    new_pc = mtvec_pc;
        //    stall = 6'b000000;
        //    flush = 1'b1;
        end else if(ret) begin
            new_pc = epc;
            flush = 1'b0;
            stall = 6'b000000;
        end else if(stall_from_mem) begin
            new_pc = 64'd0;
            flush = 1'b0;
            stall = 6'b011111;
        end else if(stall_from_if) begin
            new_pc = 64'd0;
            flush = 1'b0;
            stall = 6'b000111;
        end else begin
            stall = 6'b000000;
            flush = 1'b0;
            new_pc = 64'd0;
        end
    end
    
endmodule